This application is related to Japanese application No. 2001-072339 filed on Mar. 14, 2001, whose priority is claimed under 35 USC xc2xa7119, the disclosure of which is incorporated by reference in its entirety.
1. Field of the Invention
The present invention relates to a process of manufacturing an electron microscopic sample and a process of analyzing a semiconductor device. In particular, it relates to a process of manufacturing an electron microscopic sample suitable for observation of a certain region on a semiconductor substrate on which a semiconductor device is in the course of its manufacture, and a process of analyzing the semiconductor device.
2. Description of Related Art
A configuration (profile) of a semiconductor device has conventionally been analyzed by the following method, for example. First, a silicon wafer on which the semiconductor device has been formed or is being formed is cleaved slightly and then a silicon wafer segment is cut out of the silicon wafer. The segment is subjected to polishing, etching by using FIB (focused ion beam) and the like to form a sample for the analysis and a plane and a section of the sample are analyzed by using a SEM (scanning electron microscope).
According to the method, however, an alignment accuracy for manufacturing the analysis sample is about xc2x10.5 mm. Therefore, it has been different to form a sample for analyzing a certain region with an accuracy less than 1 xcexcm.
In this aspect, Japanese Unexamined Patent Publication No. Hei 5(1993)-187039 proposes a process of manufacturing an electron microscopic sample with the alignment accuracy improved to about xc2x10.1 xcexcm.
According to the process, a high-speed rotary blade is aligned with a certain region of a silicon wafer on which semiconductor devices have been formed or are being formed, while observing through a high performance microscope. Then, a wafer segment including the certain region is cut out and processed by using the high speed rotary blade such that only a small surface portion remains. Thereafter, the remaining small surface portion is further thinned by using a focused-charged-particle-beam apparatus to prepare an analysis sample. In this step, to shorten a period for processing with the apparatus and to prevent damage to the analysis sample during the processing, the processing width and depth of the wafer segment are limited as small as possible.
However, since this method involves manual operations such as an absolute alignment and the etching while observing through the high performance microscope, there still remain problems such as the processing for preparing the analysis sample takes a long time.
In general, a photoresist technique has been utilized for patterning during the manufacture of a semiconductor device. According to the general photoresist technique, edges of the resulting pattern are rounded as compared with those of the intended design. As the semiconductor device is minimized, the edges of the resulting pattern are further rounded. In particular, in the case of STI (Shallow Trench Isolation) in which grooves are formed in a semiconductor substrate by the photoresist technique and an oxide film is formed in the grooves by thermal oxidation, edges of the groove are rounded and the growth speed of the oxide film depends on the plane orientation of the groove, so that the device characteristics are greatly influenced.
In view of the above-mentioned problems, the present invention has been achieved to provide a process of easily manufacturing an electron microscopic sample for analyzing a plane configuration of a semiconductor device by using an electron microscope with very high accuracy with respect to a certain region, without cleaving the wafer, and a process of analyzing the plane configuration and synthesizing data obtained by the analysis to obtain a three-dimensional configuration.
According to the present invention, provided is a process of manufacturing an electron microscopic sample comprising the steps of:
(a) forming a mask layer for covering an object region to be analyzed of a semiconductor layer and/or a conductive layer which have/has been patterned into a desired configuration;
(b) reducing a periphery region surrounded the object region to be analyzed in a depth direction by using the mask layer;
(c) removing the mask layer and forming an etch stop layer over the object region to be analyzed and the periphery region; and
(d) polishing the semiconductor layer and/or the conductive layer in the object region to be analyzed down to the level of the surface of etch stop layer lying on the reduced periphery region.
Further, according to the present invention, provided is a process of analyzing a semiconductor device wherein a plurality of plane configurations of the semiconductor device are observed by using an electron microscopic sample obtained by the above-described process and the obtained data is synthesized to analyze a three-dimensional configuration of the semiconductor device.
These and other objects of the present application will become more readily apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.